Altera DisplayPort MegaCore Function User Manual
Page 26
Table 4-6: Secondary Interface
N
is the stream number; for example,
tx_msa_conduit
represents Stream 0,
tx1_msa_conduit
represents Stream
1, and so on.
Interface
Signal Type Clock Domain
Port
Direction
Description
tx_ss_clk Clock
N/A
tx_ss_clk
Output
TX transceiver clock
out and clock for
secondary stream
MSA
(txN_
msa_
conduit)
Conduit
tx_ss_clk
txN_msa[191:0]
Input
Input port for fixed
MSA parameters
Secondary
Stream
(txN_ss)
AV-ST
tx_ss_clk
txN_ss_data[127:0]
Input
Secondary stream
interface
txN_ss_valid
Input
txN_ss_ready
Outp
ut
txN_ss_sop
Input
txN_ss_eop
Input
Table 4-7: Audio Interface
m
is the number of TX audio channels.
N
is the stream number; for example,
tx_audio
represents Stream 0,
tx1_audio
represents Stream 1, and so on.
Interface
Signal Type
Clock
Domain
Port
Direction
Description
Audio
(txN_audio)
Clock
N/A
txN_audio_clk
Input
Audio clock
Conduit
txN_audio_
clk
txN_audio_lpcm_data
[m*32-1:0]
Input
Audio sample data
interface
txN_audio_valid
Input
txN_audio_mute
Input
4-10
Source Interfaces
UG-01131
2015.05.04
Altera Corporation
DisplayPort Source
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
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- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
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- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
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- FFT MegaCore Function (50 pages)
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- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
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- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
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- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
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- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
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