Dprx0_aud_aif4, Sink mst registers, Dprx0_aud_aif4 -16 – Altera DisplayPort MegaCore Function User Manual
Page 167: Sink mst registers -16
Direction: RO
Reset: 0×00000000
Table 10-30: DPRX0_AUD_AIF3 Bits
Bit
Bit Name
Function
31:8
Unused
7:0
AIF
Received audio InfoFrame byte 3 (refer to CEA-861-E
specification)
DPRX0_AUD_AIF4
Received audio InfoFrame register,
DPRX0_AUD_AIF4
.
Address: 0×0036
Direction: R0
Reset: 0×00000000
Table 10-31: DPRX0_AUD_AIF4 Bits
Bit
Bit Name
Function
31:8
Unused
7:0
AIF
Received audio InfoFrame byte 4 (refer to CEA-861-E
specification)
Sink MST Registers
MST controller control.
Address: 0×00a0
Direction: RW
Reset: 0×00000000
Table 10-32: DPRX_MST_CONTROL1 Bits
Bit
Bit Name
Function
31
VCPTAB_UPD_FORCE
This flag always reads back at 0.
1 = Force VC payload ID table update.
30
VCPTAB_UPD_REQ
• 1 = Request for VC payload ID table
update
• 0 = No change to VC payload ID table
10-16
DPRX0_AUD_AIF4
UG-01131
2015.05.04
Altera Corporation
DisplayPort Sink Register Map and DPCD Locations
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