Dptx_mst_vcptab3, Dptx_mst_vcptab4, Dptx_mst_vcptab3 -17 – Altera DisplayPort MegaCore Function User Manual
Page 138: Dptx_mst_vcptab4 -17
DPTX_MST_VCPTAB3
VC Payload ID Table
Address: 0×00a5
Direction: RW
Reset: 0×00000000
Table 9-33: DPTX_MST_VCPTAB3 Bits
Bit
Bit Name
Function
31:28
VCPSLOT31
VC payload ID or slot 31
27:24
VCPSLOT30
VC payload ID or slot 30
23:20
VCPSLOT29
VC payload ID or slot 29
19:16
VCPSLOT28
VC payload ID or slot 28
15:12
VCPSLOT27
VC payload ID or slot 27
11:8
VCPSLOT26
VC payload ID or slot 26
7:4
VCPSLOT25
VC payload ID or slot 25
3:0
VCPSLOT24
VC payload ID or slot 24
DPTX_MST_VCPTAB4
VC Payload ID Table
Address: 0×00a6
Direction: RW
Reset: 0×00000000
Table 9-34: DPTX_MST_VCPTAB4 Bits
Bit
Bit Name
Function
31:28
VCPSLOT39
VC payload ID or slot 39
27:24
VCPSLOT38
VC payload ID or slot 38
23:20
VCPSLOT37
VC payload ID or slot 37
19:16
VCPSLOT36
VC payload ID or slot 36
15:12
VCPSLOT35
VC payload ID or slot 35
UG-01131
2015.05.04
DPTX_MST_VCPTAB3
9-17
DisplayPort Source Register Map and DPCD Locations
Altera Corporation
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