Altera DisplayPort MegaCore Function - Manual (Page 37)

DisplayPort Sink
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2015.05.04
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Sink Overview
The DisplayPort sink has a scalable main link with 1, 2, or 4 lanes for a total up to 21.6 Gbps bandwidth. A
bidirectional AUX channel with 1 Mbps Manchester encoding provides side-band communication. The
sink drives a hot plug detect (HPD) signal to notify the source that a sink is present. Additionally, it
provides an interrupt mechanism so that the sink can get the source’s attention.
Figure 5-1: DisplayPort Sink Block Diagram
Source
Lane 0 Data (1.62, 2.7, or 5.4 Gbps)
Lane 1 Data (1.62, 2.7, or 5.4 Gbps)
Lane 2 Data (1.62, 2.7, or 5.4 Gbps)
Lane 3 Data (1.62, 2.7, or 5.4 Gbps)
AUX Channel (1 Mbps)
Hot Plug Detect
Sink
The main link has three selectable data rates: 1.62, 2.7, and 5.4 Gbps. The source device sets the lane count
and link rate combination (referred to as the policy) according to the sink’s capabilities and required
video bandwidth.
The AUX channel is an AC-coupled differential pair for bidirectional communication. The signaling is a
self-clocked Manchester encoding at 1 Mbps. Like 100-T Ethernet, the encoder uses a preceding synchro‐
nization pattern in each 16-byte maximum packet. The AUX channel uses a master/slave hierarchy in
which the source (master) initiates all communication.
Sink Functional Description
The DisplayPort sink has a complete set of parameters for optimizing device resources.
The DisplayPort sink consists of a DisplayPort decoder block, a transceiver management block, and a
controller interface block with an Avalon-MM interface for connecting with an embedded controller such
as the Nios II processor. You can configure the ports using an RTL wrapper instantiation or
implementing the IP core as a Qsys component.
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