Altera DisplayPort MegaCore Function - Manual (Page 122)

DisplayPort Source Register Map and DPCD
Locations
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DisplayPort source instantiations require an embedded controller (Nios II processor or another
controller) to act as the policy maker.
Table 9–1 describes the notation used to describe the registers.
Table 9-1: Notation
Shorthand Definition
RW Read/write
RO Read only
WO Write only
CRO Clear on read or write, read only
CWO Clear on read or write, write only
Source General Registers
This section describes the general registers.
DPTX_TX_CONTROL
The IRQ is asserted when
AUX_IRQ_EN
= 1 and in register
DPTX_AUX_CONTROL
flag
MSG_READY
= 1. IRQ is
de-asserted by setting
AUX_IRQ_EN
to 0 or reading from
DPTX_AUX_COMMAND
. IRQ is also asserted if
HPD_IRQ_EN
= 1 and a new HPD event is detected (
HPD_EVENT
in register
DPTX_TX_STATUS
different from
00). IRQ is de-asserted by setting
HPD_IRQ_EN
to 0 or reading from
DPTX_TX_STATUS
.
The
TX_LINK_RATE
drives the respective
tx_reconfig
port. Setting
LANE_COUNT
to 00000 causes the
transmitter GXB to always send a logical zero (i.e., a constant voltage level). You can use this function to
cause a “power down” for link layer compliance testing.
Address: 0x0000
Direction: RW
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