Altera DisplayPort MegaCore Function - Manual (Page 85)

Table 6-6: Hardware Demonstration Files
Files are named with <prefix>_<name>.<extension> where <prefix> represents the device (av for Arria V devices,
cv for Cyclone V devices, and sv for Stratix V devices).
File Type File Description
Verilog HDL
design files
top.v Top-level design file.
bitec_reconfig_alt_ .v Reconfiguration manager top-level. This
module is a high-level FSM that generates the
control signals to reconfigure the VOD and
pre-emphasis, selects the PLL reference clock,
and reconfigures clock divider setting. It loops
through all the channels and transceiver
settings.
altera_pll_reconfig_core.v
altera_pll_reconfig_mif_reader.v
altera_pll_reconfig_top.v
bitec_cc_fifo.v
bitec_cc_pulse.v
bitec_clkrev.v
bitec_fpll_cntrl.v
bitec_fpll_reconf.v
bitec_loop_cntrl.v
bitec_vsyncgen.v
clkrec_pll_ .v
Clock recovery core encrypted design files.
IP Catalog files video_pll .v
pll_135.v
gxb_reconfig.v
gxb_reset.v
gxb_rx.v
gxb_tx.v
IP Catalog variants for the various helper IP
cores.
Qsys system control.qsys Qsys system file.
6-24 Copy the Design Files to Your Working Directory
UG-01131
2015.05.04
Altera Corporation DisplayPort IP Core Hardware Demonstration
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