Altera DisplayPort MegaCore Function User Manual
Page 151
Location Name
Address
PAYLOAD_ALLOCATE_START_TIME_SLOT
0×01C1
PAYLOAD_ALLOCATE_TIME_SLOT_COUNT
0×01C2
SINK_COUNT
0×0200
DEVICE_SERVICE_IRQ_VECTOR
0×0201
LANE0_1_STATUS
0×0202
LANE2_3_STATUS
0×0203
LANE_ALIGN_STATUS_UPDATED
0×0204
SINK_STATUS
0×0205
ADJUST_REQUEST_LANE0_1
0×0206
ADJUST_REQUEST_LANE2_3
0×0207
SYMBOL_ERROR_COUNT_LANE0
0×0210
SYMBOL_ERROR_COUNT_LANE1
0×0212
SYMBOL_ERROR_COUNT_LANE2
0×0214
SYMBOL_ERROR_COUNT_LANE3
0×0216
TEST_REQUEST
0×0218
TEST_LINK_RATE
0×0219
TEST_LANE_COUNT
0×0220
PHY_TEST_PATTERN
0×0248
TEST_80BIT_CUSTOM_PATTERN (0×0250 to 0×0259)
0×0250
TEST_RESPONSE
0×0260
TEST_EDID_CHECKSUM
0×0261
PAYLOAD_TABLE_UPDATE_STATUS
0×02C0
VC_PAYLOAD_ID_SLOT_1 (0×02C1 to 0×02FF)
0×02C1
SET_POWER_STATE
0×0600
DOWN_REQ (0×1000 to 0×102F)
0×1000
UP_REP (0×1200 to 0×122F)
0×1200
DOWN_REP (0×1400 to 0×142F)
0×1400
UP_REQ (0×1600 to 0×162F)
0×1600
9-30
Source-Supported DPCD Locations
UG-01131
2015.05.04
Altera Corporation
DisplayPort Source Register Map and DPCD Locations
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)