Altera DisplayPort MegaCore Function - Manual (Page 159)

Reset: 0×00000000
Table 10-8: DPRX_BER_CNTI0 Bits
Bit Bit Name Function
31 Unused
30:16 CNT1 Symbol error counter for lane 1
15 Unused
14:0 CNT0 Symbol error counter for lane 0
These registers are meant for internal use and are not exposed in the DPCD.
DPRX_BER_CNTI1
Bit-error counter register for lane 2 and lane 3.
Address: 0×0007
Direction: RO
Reset: 0×00000000
Table 10-9: DPRX_BER_CNTI1 Bits
Bit Bit Name Function
31 Unused
30:16 CNT3 Symbol error counter for lane 3
15 Unused
14:0 CNT2 Symbol error counter for lane 2
These registers are meant for internal use and are not exposed in the DPCD.
Sink MSA Registers
The MSA registers are allocated at addresses:
• 0×0020 through 0×002f for Stream 0
• 0×0040 through 0×004f for Stream 1
• 0×0060 through 0×006f for Stream 2
• 0×0080 through 0×008f for Stream 3
Note: Only registers for Stream 0 are listed in the following sections. Registers for Stream 0 are also
available in non-controller mode.
10-8 DPRX_BER_CNTI1
UG-01131
2015.05.04
Altera Corporation DisplayPort Sink Register Map and DPCD Locations
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