Altera DisplayPort MegaCore Function User Manual
Page 189
Location Name
Address
Without
Controller
With Controller
IEEE_OUI
0×0401
—
Yes
IEEE_OUI
0×0402
—
Yes
DEVICE_IDENTIFICATION_STRING
0×0403
—
Yes
HARDWARE_REVISION
0×0409
—
Yes
FWSW_MAJOR
0×040A
—
Yes
FWSW_MINOR
0×040B
—
Yes
RESERVED (0x040C to 0x04FF)
0×040C
—
Yes
IEEE_OUI
0×0500
Yes
Yes
IEEE_OUI
0×0501
Yes
Yes
IEEE_OUI
0×0502
Yes
Yes
DEVICE_IDENTIFICATION_STRING
0×0503
—
Yes
HARDWARE_REVISION
0×0509
—
Yes
FWSW_MAJOR
0×050A
—
Yes
FWSW_MINOR
0×050B
—
Yes
RESERVED (0x050C to 0x05FF)
0×050C
—
Yes
SET_POWER_STATE
0×0600
Yes
Yes
DOWN_REQ (0x1000 to 0x102F)
0×1000
—
Yes
DOWN_REP (0x1400 to 0x142F)
0×1400
—
Yes
SINK_COUNT_ESI
0×2002
—
Yes
DEVICE_SERVICE_IRQ_VECTOR_ESI0
0×2003
—
Yes
DEVICE_SERVICE_IRQ_VECTOR_ESI1
0×2004
—
Yes
LINK_SERVICE_IRQ_VECTOR_ESI0
0×2005
—
Yes
LANE0_1_STATUS
0×200C
—
Yes
10-38
Sink-Supported DPCD Locations
UG-01131
2015.05.04
Altera Corporation
DisplayPort Sink Register Map and DPCD Locations
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)