Altera DisplayPort MegaCore Function User Manual
Page 185
Location Name
Address
Without
Controller
With Controller
EDP_CONFIGURATION_CAP
0×000D
—
Yes
TRAINING_AUX_RD_INTERVAL
0×000E
—
Yes
ADAPTER_CAP
0×000F
—
Yes
FAUX_CAP
0×0020
—
Yes
MST_CAP
0×0021
—
Yes
NUMBER_OF_AUDIO_ENDPOINTS
0×0022
—
Yes
GUID
0×0030
—
Yes
DWN_STRM_PORTX_CAP
0×0080
Yes
Yes
LINK_BW_SET
0×0100
Yes
Yes
LANE_COUNT_SET
0×0101
Yes
Yes
TRAINING_PATTERN_SET
0×0102
Yes
Yes
TRAINING_LANE0_SET
0×0103
Yes
Yes
TRAINING_LANE1_SET
0×0104
Yes
Yes
TRAINING_LANE2_SET
0×0105
Yes
Yes
TRAINING_LANE3_SET
0×0106
Yes
Yes
DOWNSPREAD_CTRL
0×0107
Yes
Yes
MAIN_LINK_CHANNEL_CODING_SET
0×0108
Yes
Yes
I2C_SPEED_CONTROL
0×0109
—
Yes
EDP_CONFIGURATION_SET
0×010A
—
Yes
LINK_QUAL_LANE0_SET
0×010B
—
Yes
LINK_QUAL_LANE1_SET
0×010C
—
Yes
LINK_QUAL_LANE2_SET
0×010D
—
Yes
LINK_QUAL_LANE3_SET
0×010E
—
Yes
10-34
Sink-Supported DPCD Locations
UG-01131
2015.05.04
Altera Corporation
DisplayPort Sink Register Map and DPCD Locations
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)