Displayport ip core hardware demonstration, Displayport ip core hardware demonstration -1 – Altera DisplayPort MegaCore Function User Manual
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DisplayPort IP Core Hardware Demonstration
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2015.05.04
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The Altera DisplayPort hardware demonstration evaluates the functionality of the DisplayPort IP core
and provides a starting point for you to create your own design. The example design uses a fully
functional OpenCore Plus evaluation version, giving you the freedom to explore the core and understand
its performance in hardware.
The design is 4Kp60 capable and performs a loop-through for a standard DisplayPort video stream. You
connect a DisplayPort-enabled device—such as a graphics card with DisplayPort interface—to the
Transceiver Native PHY RX, and the DisplayPort sink input. The DisplayPort sink decodes the port into a
standard video stream and sends it to the clock recovery core. The clock recovery core synthesizes the
original video pixel clock to be transmitted together with the received video data. You require the clock
recovery feature to produce video without using a frame buffer. The clock recovery core then sends the
video data to the DisplayPort source, and the Transceiver Native PHY TX. The DisplayPort source port of
the HSMC daughter card transmits the image to a monitor.
Note: If you use another Altera development board, you must change the device assignments and the pin
assignments. You make these changes in the
assignments.tcl
file. If you use another DisplayPort
daughter card, you must change the pin assignments, Qsys system, and software.
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