Altera DisplayPort MegaCore Function - Manual (Page 46)

Interface Port Type Clock Domain Port Direction Description
EDID
(rx_edid)
AV-MM
aux_clk
rx_edid_address[7:0] Output
Avalon-MM master
interface to external
on-chip memory for
EDID
rx_edid_read Outp
ut
rx_edid_write Outp
ut
rx_edid_writedata[7:0] Outp
ut
rx_edid_readdata[7:0] Input
rx_edid_waitrequest Input
Table 5-6: Debugging Interface
s
is the number of symbols per clock and
N
is the stream number.
Interface Signal Type Clock
Domain
Port Direction Description
Link Parameters
(rx_params)
Conduit
aux_clk
rx_lane_count[4:0] Output Sink current link lane
count value
Debugging
(rxN_stream)
Conduit
rx_ss_clk
rxN_stream_
data[4*8*s–1:0]
Output
Raw symbol output
stream
rxN_stream_ctrl[4*s–
1:0]
Outp
ut
rxN_stream_valid Outp
ut
rxN_stream_clk Outp
ut
Table 5-7: Secondary Interface
N
is the stream number; for example,
rx_msa_conduit
represents Stream 0,
rx1_msa_conduit
represents Stream
1, and so on .
Interface Signal Type Clock Domain Port Direction Description
rx_ss_clk Clock N/A rx_ss_clk Output Clock
5-10 Sink Interfaces
UG-01131
2015.05.04
Altera Corporation DisplayPort Sink
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