Dptx_mst_vcptab7, Dptx_mst_vcptab7 -19 – Altera DisplayPort MegaCore Function User Manual
Page 140
Table 9-36: DPTX_MST_VCPTAB6 Bits
Bit
Bit Name
Function
31:28
VCPSLOT55
VC payload ID or slot 55
27:24
VCPSLOT54
VC payload ID or slot 54
23:20
VCPSLOT53
VC payload ID or slot 53
19:16
VCPSLOT52
VC payload ID or slot 52
15:12
VCPSLOT51
VC payload ID or slot 51
11:8
VCPSLOT50
VC payload ID or slot 50
7:4
VCPSLOT49
VC payload ID or slot 49
3:0
VCPSLOT48
VC payload ID or slot 48
DPTX_MST_VCPTAB7
VC Payload ID Table
Address: 0×00a9
Direction: RW
Reset: 0×00000000
Table 9-37: DPTX_MST_VCPTAB7 Bits
Bit
Bit Name
Function
31:28
VCPSLOT63
VC payload ID or slot 63
27:24
VCPSLOT62
VC payload ID or slot 62
23:20
VCPSLOT61
VC payload ID or slot 61
19:16
VCPSLOT60
VC payload ID or slot 60
15:12
VCPSLOT59
VC payload ID or slot 59
11:8
VCPSLOT58
VC payload ID or slot 58
7:4
VCPSLOT57
VC payload ID or slot 57
3:0
VCPSLOT56
VC payload ID or slot 56
UG-01131
2015.05.04
DPTX_MST_VCPTAB7
9-19
DisplayPort Source Register Map and DPCD Locations
Altera Corporation
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)