Altera DisplayPort MegaCore Function - Manual (Page 155)

Bit Bit Name Function
6 SYM_LOCK2 0 = Symbol unlocked (lane 2)
1 = Symbol locked (lane 2)
5 SYM_LOCK1 0 = Symbol unlocked (lane 1)
1 = Symbol locked (lane 1)
4 SYM_LOCK0 0 = Symbol unlocked (lane 0)
1 = Symbol locked (lane 0)
3 CR_LOCK3 0 = Clock unlocked (lane 3)
1 = Clock locked (lane 3)
2 CR_LOCK2 0 = Clock unlocked (lane 2)
1 = Clock locked (lane 2)
1 CR_LOCK1 0 = Clock unlocked (lane 1)
1 = Clock locked (lane 1)
0 CR_LOCK0 0 = Clock unlocked (lane 0)
1 = Clock locked (lane 0)
This register is also available in read-only mode when not using a controller.
Table 10-5: DPRX_RX_STATUS Bits(Non-Controller Mode)
Bit Bit Name Function
31:17 Unused
16 SYNC_LOSS This flag can be reset by writing it to 1:
0 = Symbol lock on all lanes in use
1 = Symbol lock lost on one or more of the used lanes
15:8 Unused
7 SYM_LOCK3 0 = Symbol unlocked (lane 3)
1 = Symbol locked (lane 3)
6 SYM_LOCK2 0 = Symbol unlocked (lane 2)
1 = Symbol locked (lane 2)
10-4 DPRX_RX_STATUS
UG-01131
2015.05.04
Altera Corporation DisplayPort Sink Register Map and DPCD Locations
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