Altera DisplayPort MegaCore Function - Manual (Page 55)

assign vid_h_sync = rx_vid_h_sync;
assign vid_de = rx_vid_valid;
assign vid_v_sync = rx_vid_v_sync;
RX Transceiver Interface
The transceiver or Native PHY IP core instance is no longer instantiated within the DisplayPort IP core.
The DisplayPort IP core uses a soft 8B/10B decoder. This interface receives RX transceiver recovered data
(
rx_parallel_data
) in either dual symbol (20-bit) or quad symbol (40-bit) mode, and drives the digital
reset (
rx_digitalreset
), analog reset (
rx_analogreset
), and controls the CDR circuitry locking mode.
Transceiver Reconfiguration Interface
You can reconfigure the transceiver to accept a single reference clock of 135 MHz for all bit rates: RBR,
HBR, and HBR2.
During run-time, you can reconfigure the transceiver to operate in either one of the bit rate by changing
RX CDR PLLs divider ratio.
When the IP core makes a request, the
rx_reconfig_req
port goes high. The user logic asserts
rx_reconfig_ack
, and then reconfigures the transceiver. During reconfiguration, the user logic holds
rx_reconfig_busy
high. The user logic drives it low when reconfiguration completes.
Note: The transceiver requires a reconfiguration controller. Reset the transceiver to a default state upon
power-up.
Related Information
• AN 645: Dynamic Reconfiguration of PMA Controls in Stratix V Devices
Provides more information about using the Transceiver Reconfiguration Controller to reconfigure the
Stratix V Physical Media Attachment (PMA) controls dynamically.
• Altera Transceiver PHY IP Core User Guide
Provides more information about how to reconfigure the transceiver for 28-nm devices.
• AN 676: Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in
Arria V and Cyclone V Devices
Provides more information about using the Transceiver Reconfiguration Controller to reconfigure the
Arria V Physical Media Attachment (PMA) controls dynamically.
• AN 678: High-Speed Link Tuning Using Signal Conditioning Circuitry
Provides more information about link tuning.
• Arria 10 Transceiver PHY User Guide
Provides more information about how to reconfigure the transceiver for Arria 10 devices.
Secondary Stream Interface
The secondary streams data can be received through the
rxN_ss
interfaces. The interfaces do not allow for
back-pressure and assume the downstream logic can handle complete packets. The
rxN_ss
interface does
not distinguish between the types of packets it receives.
The format of the
rxN_ss
interface output corresponds to four 15-nibble code words as specified by the
DisplayPort 1.2a specification section 2.2.6.3. These 15-nibble code words are typically supplied to the
UG-01131
2015.05.04
RX Transceiver Interface 5-19
DisplayPort Sink Altera Corporation
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