Dprx0_msa_misc1, Dprx0_vbid, Dprx0_msa_misc1 -13 – Altera DisplayPort MegaCore Function User Manual
Page 164: Dprx0_vbid -13
Table 10-22: DPRX0_MSA_MISC0 Bits
Bit
Bit Name
Function
31:8
Unused
7:0
MISC0
Main stream attribute MISC0
DPRX0_MSA_MISC1
Address: 0×002d
Direction: RO
Reset: 0×00000000
Table 10-23: DPRX0_MSA_MISC1 Bits
Bit
Bit Name
Function
31:8
Unused
7:0
MISC1
Main stream attribute MISC1
DPRX0_VBID
VB-ID register,
DPRX0_VBID
.
Address: 0×002e
Direction: RO
Reset: 0×00000000
Table 10-24: DPRX0_VBID Bits
Bit
Bit Name
Function
31:8
Unused
7
MSA_LOCK
0 = MSA unlocked
1 = MSA locked (on all lanes)
6
VBID_LOCK
0 = VB-ID unlocked
1 = VB-ID locked (on all lanes)
5:0
VBID
VB-ID flags (refer to the DisplayPort specification)
UG-01131
2015.05.04
DPRX0_MSA_MISC1
10-13
DisplayPort Sink Register Map and DPCD Locations
Altera Corporation
See also other documents in the category Altera Measuring instruments:
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)