Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 99)

Chapter 6: Functional Description—High-Performance Controller II 6–5
Controller Features Descriptions
June 2011 Altera Corporation External Memory Interface Handbook Volume 3
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
Since the controller can reorder transactions for best efficiency, when you assert the
local_autopch_req
signal, the controller evaluates the current command and
buffered commands to determine the best autoprecharge operation.
Address and Command Decoding Logic
When the main state machine issues a command to the memory, it asserts a set of
internal signals. The address and command decoding logic turns these signals into
AFI-specific commands and address. This block generates the following signals:
■ Clock enable and reset signals: afi_cke, afi_rst_n
■ Command and address signals: afi_cs_n, afi_ba, afi_addr, afi_ras_n,
afi_cas_n
, afi_we_n
Low-Power Logic
There are two types of low-power logic: the user-controlled self-refresh logic and
automatic power-down with programmable time-out logic.
User-Controlled Self-Refresh
When you assert the local_self_rfsh_req signal, the controller completes any
currently executing reads and writes, and then interrupts the command queue and
immediately places the memory into self-refresh mode. When the controller places the
memory into self-refresh mode, it responds by asserting an acknowledge signal,
local_self_rfsh_ack
. You can leave the memory in self-refresh mode for as long as
you choose.
To bring the memory out of self-refresh mode, you must deassert the request signal,
and the controller responds by deasserting the acknowledge signal when the memory
is no longer in self-refresh mode.
1 If a user-controlled refresh request and a system-generated refresh request occur at
the same time, the user-controlled refresh takes priority; the system-generated refresh
is processed only after the user-controlled refresh request is completed.
Automatic Power-Down with Programmable Time-Out
The controller automatically places the memory in power-down mode to save power
if the requested number of idle controller clock cycles is observed in the controller.
The Auto Power Down Cycles parameter on the Controller Settings tab allows you
to specify a range between 1 to 65,535 idle controller clock cycles. The counter for the
programmable time-out starts when there are no user read or write requests in the
command queue. Once the controller places the memory in power-down mode, it
responds by asserting the acknowledge signal, local_powerdown_ack.
ODT Generation Logic
The on-die termination (ODT) generation logic generates the necessary ODT signals
for the controller, based on the scheme that Altera recommends.