Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 75)

Chapter 5: Functional Description—ALTMEMPHY 5–29
ALTMEMPHY Signals
June 2011 Altera Corporation External Memory Interface Handbook Volume 3
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
Other Signals
aux_half_rate_clk Output 1
In half-rate designs, a copy of the phy_clk_1x signal
that you can use in other parts of your design, same
as phy_clk port.
aux_full_rate_clk Output 1
In full-rate designs, a copy of the mem_clk_2x signal
that you can use in other parts of your design.
aux_scan_clk Output 1
Low frequency scan clock supplied primarily to clock
any user logic that interfaces to the PLL and DLL
reconfiguration interfaces.
aux_scan_clk_reset_n Output 1
This reset output asynchronously asserts (drives low)
when global_reset_n is asserted and de-assert
(drives high) synchronous to aux_scan_clk when
global_reset_n
is deasserted. It allows you to
reset any external circuitry clocked by
aux_scan_clk
.
Write Data Interface
ctl_dqs_burst Input
MEM_IF_DQS_WIDTH ×
DWIDTH_RATIO / 2
When asserted, mem_dqs is driven. The
ctl_dqs_burst
signal must be asserted before
ctl_wdata_valid and must be driven for the
correct duration to generate a correctly timed
mem_dqs
signal.
ctl_wdata_valid Input
MEM_IF_DQS_WIDTH ×
DWIDTH_RATIO / 2
Write data valid. Generates ctl_wdata and ctl_dm
output enables.
ctl_wdata Input
MEM_IF_DWIDTH ×
DWIDTH_RATIO
Write data input from the controller to the PHY to
generate mem_dq.
ctl_dm Input
MEM_IF_DM_WIDTH ×
DWIDTH_RATIO
DM input from the controller to the PHY.
ctl_wlat Output 5
Required write latency between address/command
and write data that is issued to ALTMEMPHY
controller local interface.
This signal is only valid when the ALTMEMPHY
sequencer successfully completes calibration, and
does not change at any point during normal
operation.
The legal range of values for this signal is 0 to 31; and
the typical values are between 0 and ten, 0 mostly for
low CAS latency DDR memory types.
Table 5–6. AFI Signals (Part 2 of 4)
Signal Name Type Width (1) Description