Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 90)

5–44 Chapter 5: Functional Description—ALTMEMPHY
Using a Custom Controller
External Memory Interface Handbook Volume 3 June 2011 Altera Corporation
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
Calibration Process Requirements
When the global reset_n signal is released, the ALTMEMPHY handles the
initialization and calibration sequence automatically. The sequencer calibrates
memory interfaces by issuing reads to multiple ranks of DDR SDRAM (multiple chip
select). Timing margins decrease as the number of ranks increases. It is impractical to
supply one dedicated resynchronization clock for each rank of memory, as it
consumes PLL resources for the relatively small benefit of improved timing margin.
When calibration is complete, the ctl_cal_success signal goes high if successful; the
ctl_cal_fail
signal goes high if calibration fails. Calibration can be repeated by the
controller using the soft_reset_n signal, which when asserted puts the sequencer
into a reset state and when released the calibration process begins again.
1
You can ignore the following two warning and critical warning messages:
Warning: Timing Analysis for multiple chip select DDR/DDR2/DDR3-SDRAM
configurations is preliminary (memory interface has a chip select width
of 4)
Critical Warning: Read Capture and Write timing analyses may not be
valid due to violated timing model assumptions
Other Local Interface Requirements
The memory burst length can be two, four, or eight for DDR SDRAM devices, and
four or eight for DDR2 SDRAM devices. For a half-rate controller, the memory clock
runs twice as fast as the clock provided to the local interface, so data buses on the local
interface are four times as wide as the memory data bus. For a full-rate controller, the
memory clock runs at the same speed as the clock provided to the local interface, so
the data buses on the local interface are two times as wide as the memory data bus.
This section describes the DDR or DDR2 SDRAM high-performance controller II with
the AFI.
Address and Command Interfacing
Address and command signals are automatically sized for 1T operation, such that for
full-rate designs there is one input bit per pin (for example, one cs_n input per
chip select configured); for half-rate designs there are two. If you require a more
conservative 2T address and command scheme, use a full-rate design and drive the
address/command inputs for two clock cycles, or in a half-rate design drive both
address/command bits for a given pin identically.
1 Although the PHY inherently supports 1T addressing, the high-performance
controller II supports only 2T addressing, so PHY timing analysis is performed
assuming 2T address and command signals.
Handshake Mechanism Between Read Commands and Read Data
When performing a read, the high-performance controller II with the AFI asserts the
ctl_doing_read
signal to indicate that a read command is requested and the byte
lanes that it expects valid data to return on. ALTMEMPHY uses the ctl_doing_read
signal for the following actions:
■ Control of the postamble circuit