Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 32)

3–6 Chapter 3: Parameter Settings
ALTMEMPHY Parameter Settings
External Memory Interface Handbook Volume 3 June 2011 Altera Corporation
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
DQ bits per DQS bit 4 or 8 bits
Defines the number of data (DQ) bits for each data strobe
(DQS) pin.
Precharge address bit 8 or 10 bits
Selects the bit of the address bus to use as the precharge
address bit.
Drive DM pins from FPGA Yes or No —
Specifies whether you are using DM pins for write
operation. Altera devices do not support DM pins in ×4
mode.
Maximum memory frequency
for CAS latency 3.0
80–533 MHz
Specifies the frequency limits from the memory data
sheet per given CAS latency. The ALTMEMPHY
parameter editor generates a warning if the operating
frequency with your chosen CAS latency exceeds this
number.
Maximum memory frequency
for CAS latency 4.0
Maximum memory frequency
for CAS latency 5.0
Maximum memory frequency
for CAS latency 6.0
Note to Table 3–3 :
(1) The range values depend on the actual memory device used.
Table 3–4. DDR2 SDRAM Initialization Options
Parameter Name Range Units Description
Memory burst length 4 or 8 beats
Sets the number of words read or written per transaction.
Memory burst length of four equates to local burst length
of one in half-rate designs and to local burst length of two
in full-rate designs.
Memory burst ordering
Sequential or
Interleaved
—
Controls the order in which data is transferred between
memory and the FPGA during a read transaction. For
more information, refer to the memory device datasheet.
Enable the DLL in the
memory devices
Yes or No —
Enables the DLL in the memory device when set to Yes.
You must always enable the DLL in the memory device as
Altera does not guarantee any ALTMEMPHY operation
when the DLL is turned off. All timings from the memory
devices are invalid when the DLL is turned off.
Memory drive strength
setting Normal or
Reduced
—
Controls the drive strength of the memory device’s output
buffers. Reduced drive strength is not supported on all
memory devices. The default option is normal.
Memory ODT setting
Disabled, 50, 75,
150
W
Sets the memory ODT value. Not available in DDR
SDRAM interfaces.
Memory CAS latency setting 3, 4, 5, 6 cycles
Sets the delay in clock cycles from the read command to
the first output data from the memory.
Table 3–3. DDR2 SDRAM Attributes Settings (Part 2 of 2)
Parameter Name Range (1) Units Description