Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 58)

5–12 Chapter 5: Functional Description—ALTMEMPHY
Block Description
External Memory Interface Handbook Volume 3 June 2011 Altera Corporation
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
■ Manages any circuit-specific reset sequencing
Each reset is an asynchronous assert and synchronous deassert on the appropriate
clock domain. The reset management design uses a standard two-register
synchronizer to avoid metastability. A unique reset metastability protection circuit for
the clock divider circuit is required because the phy_clk domain reset metastability
protection flipflops have fan-in from the soft_reset_n input, and so these registers
cannot be used.
Figure 5–3 shows the ALTMEMPHY reset management block for Arria GX,
Arria II GX, HardCopy II, Stratix II, and Stratix II GX devices. The pll_ref_clk signal
goes directly to the PLL, eliminating the need for global clock network routing. If you
are using the pll_ref_clk signal to feed other parts of your design, you must use a
global clock network for the signal. If pll_reconfig_soft_reset_en signal is held
low, the PLL reconfig is not reset during a soft reset, which allows designs targeting
HardCopy II devices to hold the PHY in reset while still accessing the PLL reconfig
block. However, designs targeting Arria GX, Arria II GX, or Stratix II devices are
expected to tie the pll_reconfig_soft_en shell to VCC to enable PLL reconfig soft
resets.