Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 45)

Chapter 4: Compiling and Simulating 4–3
Compiling the Design
June 2011 Altera Corporation External Memory Interface Handbook Volume 3
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
1 If your top-level design does not use single bit bus notation for the
single-bit memory interface signals (for example, mem_dqs rather than
mem_dqs[0]
), in the Tcl script you should change set single_bit {[0]} to
set single_bit {}.
or
■ Alternatively, to change the pin names that do not match the design, you can add a
prefix to your pin names by performing the following steps:
a. On the Assignments menu, click Pin Planner.
b. On the Edit menu, click Create/Import Megafunction.
c. Select Import an existing custom megafunction and navigate to
.ppf.
d. Type the prefix you want to use in Instance name. For example, change
mem_addr to core1_mem_addr.
3. Set the top-level entity to the top-level design.
a. On the File menu, click Open.
b. Browse to your SOPC Builder system top-level design or <variation
name>_example_top if you are using MegaWizard Plug-In Manager, and click
Open
.
c. On the Project menu, click Set as Top-Level Entity.
4. Assign the DQ and DQS pin locations.
a. You should assign pin locations to the pins in your design, so the Quartus II
software can perform fitting and timing analysis correctly.
b. Use either the Pin Planner or Assignment Editor to assign the clock source pin
manually. Also choose which DQS pin groups should be used by assigning
each DQS pin to the required pin. The Quartus II Fitter then automatically
places the respective DQ signals onto suitable DQ pins within each group.
1
To avoid no-fit errors when you compile your design, ensure that you place
the mem_clk pins to the same edge as the mem_dq and mem_dqs pins, and set
an appropriate I/O standard for the non-memory interfaces, such as the
clock source and the reset inputs, when assigning pins in your design. For
example, for DDR SDRAM select 2.5 V and for DDR2 SDRAM select 1.8 V.
Also select in which bank or side of the device you want the Quartus II
software to place them.
5. For Stratix III and Stratix IV designs, if you are using advanced I/O timing, specify
board trace models in the Device & Pin Options dialog box. If you are using any
other device and not using advanced I/O timing, specify the output pin loading
for all memory interface pins.
6. Select your required I/O driver strength (derived from your board simulation) to
ensure that you correctly drive each signal or ODT setting and do not suffer from
overshoot or undershoot.
7. To compile the design, on the Processing menu, click Start Compilation.