Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 81)

Chapter 5: Functional Description—ALTMEMPHY 5–35
PHY-to-Controller Interfaces
June 2011 Altera Corporation External Memory Interface Handbook Volume 3
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
1 Altera recommends that you use the AFI for new designs.
For half-rate designs, the address and command signals in the ALTMEMPHY
megafunction are asserted for one mem_clk cycle (1T addressing), such that there are
two input bits per address and command pin in half-rate designs. If you require a
more conservative 2T addressing, drive both input bits (of the address and command
signal) identically in half-rate designs.
For DDR3 SDRAM with the AFI, the read and write control signals are on a per-DQS
group basis. The controller can calibrate and use a subset of the available DDR3
SDRAM devices. For example, two devices out of a 64- or 72-bit DIMM, for better
debugging mechanism.
Figure 5–11. AFI PHY Connections
AFI
Controller
local_wdata
local_rdata
ctl_addr
ctl_cas_n
ctl_we_n
ctl_rdata
Admin
Sequencer
AFI PHY
mem_dqs
mem_dq
DDR3
SDRAM
Altera Device