Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 68)

5–22 Chapter 5: Functional Description—ALTMEMPHY
Block Description
External Memory Interface Handbook Volume 3 June 2011 Altera Corporation
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
Postamble Protection
The ALTMEMPHY megafunction provides the DQS postamble logic. The postamble
clock is derived from the resynchronization clock and is the negative edge of the
resynchronization clock. The ALTMEMPHY megafunction calibrates the
resynchronization clock such that it is in the center of the data-valid window. The
clock that controls the postamble logic, the postamble clock, is the negative edge of
the resynchronization clock. No additional clocks are required.
Figure 5–6 shows the
relationship between the postamble clock and the resynchronization clock.
f For more information about the postamble circuitry, refer to the External Memory
Interfaces chapter in the Stratix II Device Handbook.
Figure 5–6. Relationship Between Postamble Clock and Resynchronization Clock (Note 1)
Note to Figure 5–6 :
(1) resync_clk_2x is delayed further to allow for the I/O element (IOE) to core transition time.
resync_clk_2x
postamble_clk
H1 H2 L2 L1
dqs (90˚ shifted)
dq
Data input to resync reg's
ARST at postamble reg's
H1L1 H2L2