Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 35)

Chapter 3: Parameter Settings 3–9
ALTMEMPHY Parameter Settings
June 2011 Altera Corporation External Memory Interface Handbook Volume 3
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
Derating Memory Setup and Hold Timing
Because the base setup and hold time specifications from the memory device
datasheet assume input slew rates that may not be true for Altera devices, derate and
update the following memory device specifications in the Preset Editor dialog box:
■ t
DS
■ t
DH
■ t
IH
■ t
IS
1
For Arria II GX and Stratix IV devices, you need not derate using the Preset Editor.
You only need to enter the parameters referenced to V
REF
, and the deration is done
automatically when you enter the slew rate information on the Board Settings tab.
After derating the values, you then need to normalize the derated value because
Altera input and output timing specifications are referenced to V
REF
. However, JEDEC
base setup time specifications are referenced to V
IH
/V
IL
AC levels; JEDEC base hold
time specifications are referenced to V
IH
/V
IL
DC levels.
When the memory device setup and hold time numbers are derated and normalized
to V
REF
, update these values in the Preset Editor dialog box to ensure that your timing
constraints are correct.
For example, according to JEDEC, 400-MHz DDR2 SDRAM has the following
specifications, assuming 1V/ns DQ slew rate rising signal and 2V/ns differential slew
rate:
■ Base t
DS
= 50
■ Base t
DH
= 125
■ V
IH
(ac) = V
REF
+ 0.2 V
■ V
IH
(dc) = V
REF
+ 0.125V
■ V
IL
(ac) = V
REF
– 0.2 V
■ V
IL
(dc) = V
REF
– 0.125 V
1 JEDEC lists two different sets of base and derating numbers for t
DS
and t
DH
specifications, whether you are using single-ended or differential DQS signaling, for
any DDR2 SDRAM components with a maximum frequency up to 267 MHz. In
addition, the V
IL
(ac) and V
IH
(ac) values may also be different for those devices.
The V
REF
referenced setup and hold signals for a rising edge are:
t
DS
(V
REF
) = Base t
DS
+ delta t
DS
+ (V
IH
(ac) – V
REF
)/slew_rate = 50 + 0 + 200 =
250 ps
t
DH
(V
REF
) = Base t
DH
+ delta t
DH
+ (V
IH
(dc) – V
REF
)/slew_rate = 125 + 0 + 67.5 =
192.5 ps
If the output slew rate of the write data is different from 1V/ns, you have to first
derate the t
DS
and t
DH
values, then translate these AC/DC level specs to V
REF
specification.