Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 106)

6–12 Chapter 6: Functional Description—High-Performance Controller II
Top-Level Signals Description
External Memory Interface Handbook Volume 3 June 2011 Altera Corporation
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
Table 6–7 on page 6–13 shows the controller local interface signals.
aux_half_rate_clk Output
An alternative clock that the PHY provides to the user. This clock
always runs at half the frequency as the external memory interface. In
full-rate designs, this clock is half the frequency of the phy_clk and
you can use it, for example to clock the user side of a half-rate bridge.
In half-rate designs, or if the Enable Half Rate Bridge option is turned
on. The same PLL output that drives the phy_clk signal drives this
clock.
dll_reference_clk Output Reference clock to feed to an externally instantiated DLL.
reset_request_n Output
Reset request output that indicates when the PLL outputs are not
locked. Use this signal as a reset request input to any system-level
reset controller you may have. This signal is always low when the PLL
is trying to lock, and so any reset logic using Altera advises you detect
a reset request on a falling edge rather than by level detection.
soft_reset_n Input
Edge detect reset input for SOPC Builder or for control by other
system reset logic. Assert to cause a complete reset to the PHY, but
not to the PLL that the PHY uses.
seriesterminationcontrol
Input (for OCT
slave)
Required signal for PHY to provide series termination calibration
value. Must be connected to a user-instantiated OCT control block
(alt_oct) or another UniPHY instance that is set to OCT master mode.
Output(for
OCT master)
Unconnected PHY signal, available for sharing with another PHY.
parallelterminationcontrol
Input (for OCT
slave)
Required signal for PHY to provide series termination calibration
value. Must be connected to a user-instantiated OCT control block
(alt_oct) or another UniPHY instance that is set to OCT master mode.
Output (for
OCT master)
Unconnected PHY signal, available for sharing with another PHY.
oct_rdn
Input (for OCT
master)
Must connect to calibration resistor tied to GND on the appropriate
RDN pin on the device. (Refer to appropriate device handbook.)
oct_rup
Input (for OCT
master)
Must connect to calibration resistor tied to V
ccio
on the appropriate
RUP pin on the device. (See appropriate device handbook.)
dqs_delay_ctrl_import Input
Allows the use of DLL in another PHY instance in this PHY instance.
Connect the export port on the PHY instance with a DLL to the
import
port on the other PHY instance.
Table 6–6. Clock and Reset Signals (Part 2 of 2)
Name Direction Description