Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 116)

6–22 Chapter 6: Functional Description—High-Performance Controller II
Register Maps
External Memory Interface Handbook Volume 3 June 2011 Altera Corporation
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
Register Maps
Table 6–13 shows the overall register mapping for the DDR and DDR2 SDRAM
Controllers with ALTMEMPHY.
ALTMEMPHY Register Map
The ALYMEMPHY register map allows you to control the memory components’
mode register settings.
Table 6–14 shows the register map for ALYMEMPHY.
To access the ALTMEMPHY register map, connect the ALTMEMPHY debug interface
signals using the Avalon-MM protocol. After configuring the ALTMEMPHY register
map, initialize a calibration request by setting bit 2 in the CSR register map address
0x100 for the mode register settings to take effect.
Table 6–13. Register Map
Address Description
ALTMEMPHY Register Map
0x005 Mode register 0-1.
0x006 Mode register 2-3.
Controller Register Map
0x100 ALTMEMPHY status and control register.
0x110 Controller status and configuration register.
0x120 Memory address size register 0.
0x121 Memory address size register 1.
0x122 Memory address size register 2.
0x123 Memory timing parameters register 0.
0x124 Memory timing parameters register 1.
0x125 Memory timing parameters register 2.
0x126 Memory timing parameters register 3.
0x130 ECC control register.
0x131 ECC status register.
0x132 ECC error address register.