Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 110)

6–16 Chapter 6: Functional Description—High-Performance Controller II
Top-Level Signals Description
External Memory Interface Handbook Volume 3 June 2011 Altera Corporation
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
Table 6–8 shows the controller interface signals.
local_ready Output
The local_ready signal indicates that the controller is ready to accept
request signals. If controller asserts the local_ready signal in the clock
cycle that it asserts a read or write request, the controller accepts that
request. The controller deasserts the local_ready signal to indicate that it
cannot accept any more requests. The controller can buffer eight read or
write requests, after which the local_ready signal goes low.
local_refresh_ack Output
Refresh request acknowledge, which the controller asserts for one clock
cycle every time it issues a refresh. Even if you do not turn on Enable User
Auto-Refresh Controls, local_refresh_ack still indicates to the local
interface that the controller has just issued a refresh command.
local_self_rfsh_ack Output
Self refresh request acknowledge signal. The controller asserts and deasserts
this signal in response to the local_self_rfsh_req signal.
local_power_down_ack Output
Auto power-down acknowledge signal. The controller asserts this signal for
one clock cycle every time auto power-down is issued.
ecc_interrupt Output
Interrupt signal from the ECC logic. The controller asserts this signal when
the ECC feature is turned on, and the controller detects an error.
Table 6–7. Local Interface Signals (Part 4 of 4)
Signal Name Direction Description
Table 6–8. Interface Signals (Part 1 of 2)
Signal Name Direction Description
mem_dq[] Bidirectional
Memory data bus. This bus is half the width of the local read and write data
busses.
mem_dqs[] Bidirectional
Memory data strobe signal, which writes data into the DDR3 SDRAM and
captures read data into the Altera device.
mem_dqs_n[] Bidirectional
Inverted memory data strobe signal, which with the mem_dqs signal improves
signal integrity.
mem_clk Bidirectional Clock for the memory device.
mem_clk_n Bidirectional Inverted clock for the memory device.
mem_addr[] Output Memory address bus.
mem_ac_parity (1) Output
Address or command parity signal generated by the PHY and sent to the
DIMM. DDR3 SDRAM only.
mem_ba[] Output Memory bank address bus.
mem_cas_n Output Memory column address strobe signal.
mem_cke[] Output Memory clock enable signals.
mem_cs_n[] Output Memory chip select signals.
mem_dm[] Output Memory data mask signal, which masks individual bytes during writes.
mem_odt Output Memory on-die termination control signal.
mem_ras_n Output Memory row address strobe signal.
mem_we_n Output Memory write enable signal.
parity_error_n (1) Output
Active-low signal that is asserted when a parity error occurs and stays
asserted until the PHY is reset. DDR3 SDRAM only