Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 24)

2–10 Chapter 2: Getting Started
Generated Files
External Memory Interface Handbook Volume 3 June 2011 Altera Corporation
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
Table 2–5 shows the additional files generated by the high-performance controller II
that may be in your project directory.
<variation_name>_alt_mem_phy_oc
t_delay
DDR2/DDR SDRAM
ALTMEMPHY variation when
dynamic OCT is enabled.
Generates the proper delay and duration for the
OCT signals.
<variation_name>_alt_mem_phy_po
stamble DDR2/DDR SDRAM
ALTMEMPHY variations Generates the postamble enable and disable
scheme for DDR and DDR2 SDRAM PHYs.
<variation_name>_alt_mem_phy_re
ad_dp
All ALTMEMPHY variations
(unused for Stratix III or
Stratix IV devices) Takes read data from the I/O through a read path
FIFO buffer, to transition from the
resyncronization clock to the PHY clock.
<variation_name>_alt_mem_phy_re
ad_dp_group
DDR2/DDR SDRAM
ALTMEMPHY variations
(Stratix III and Stratix IV
devices only)
A per DQS group version of
<variation_name>_alt_mem_phy_read_dp.
<variation_name>_alt_mem_phy_rd
ata_valid DDR2/DDR SDRAM
ALTMEMPHY variations Generates read data valid signal to sequencer and
controller.
<variation_name>_alt_mem_phy_se
q_wrapper
All ALTMEMPHY variations Generates sequencer for DDR and DDR2 SDRAM.
<variation_name>_alt_mem_phy_wr
ite_dp
All ALTMEMPHY variations
Generates the demultiplexing of data from
half-rate to full-rate DDR data.
<variation_name>_alt_mem_phy_wr
ite_dp_fr DDR2/DDR SDRAM
ALTMEMPHY variations
A full-rate version of
<variation_name>_alt_mem_phy_
write_dp
.
Table 2–4. Modules in <variation_name>_alt_mem_phy.v File (Part 2 of 2)
Module Name Usage Description
Table 2–5. Controller-Generated Files (Part 1 of 2)
Filename Description
alt_mem_ddrx_addr_cmd.v
Decodes internal protocol-related signals into memory address and
command signals.
alt_mem_ddrx_addr_cmd_wrap.v A wrapper that instantiates the alt_mem_ddrx_addr_cmd.v file.
alt_mem_ddrx_ddr2_odt_gen.v
Generates the on-die termination (ODT) control signal for DDR2
memory interfaces.
alt_mem_ddrx_ddr3_odt_gen.v
Generates the on-die termination (ODT) control signal for DDR3
memory interfaces.
alt_mem_ddrx_odt_gen.v
Wrapper that instantiates alt_mem_ddrx_ddr2_odt_gen.v and
alt_mem_ddrx_ddr3_odt_gen.v. This file also controls the ODT
addressing scheme.
alt_mem_ddrx_rdwr_data_tmg.v Decodes internal data burst related signals to memory data signals.
alt_mem_ddrx_arbiter.v
Contains logic that determines which command to execute based on
certain schemes.
alt_mem_ddrx_burst_gen.v Converts internal DRAM-aware commands to AFI signals.
alt_mem_ddrx_cmd_gen.v Converts user requests to DRAM-aware commands.
alt_mem_ddrx_csr.v Contains configuration registers.
alt_mem_ddrx_buffer.v Contains buffer for local data.
alt_mem_ddrx_buffer_manager.v Manages the allocation of buffers.