Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 40)

3–14 Chapter 3: Parameter Settings
DDR or DDR2 SDRAM Controller with ALTMEMPHY Parameter Settings
External Memory Interface Handbook Volume 3 June 2011 Altera Corporation
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
Controller Settings
1 This section describes parameters for the High Performance Controller II (HPC II)
with advanced features introduced in version 11.0 for designs generated in version
11.0. Designs created in earlier versions and regenerated in version 11.0 do not inherit
the new advanced features; for information on parameters for HPC II without the
version 11.0 advanced features, refer to the External Memory Interface Handbook for
Quartus II version 10.1, available in the
External Memory Interfaces section of the Altera
Literature website.
Table 3–8 shows the options provided in the Controller Settings tab.
Table 3–8. Controller Settings (Part 1 of 2)
Parameter Description
Controller architecture Specifies the controller architecture.
Enable self-refresh controls
Turn on to enable the controller to allow you to have control on when to place the external
memory device in self-refresh mode, refer to
“User-Controlled Self-Refresh” on page 6–5 .
Enable power down controls
Turn on to enable the controller to allow you to have control on when to place the external
memory device in power-down mode.
Enable auto power down
Turn on to enable the controller to automatically place the external memory device in
power-down mode after a specified number of idle controller clock cycles is observed in the
controller. You can specify the number of idle cycles after which the controller powers down
the memory in the Auto Power Down Cycles field, refer to
“Automatic Power-Down with
Programmable Time-Out” on page 6–5 .
Auto power down cycles
Determines the desired number of idle controller clock cycles before the controller places
the external memory device in a power-down mode. The legal range is 1 to 65,535.
The auto power-down mode is disabled if you set the value to 0 clock cycles.
Enable user auto-refresh
controls
Turn on to enable the controller to allow you to issue a single refresh.
Enable auto-precharge
control
Turn on to enable the auto-precharge control on the controller top level. Asserting the
auto-precharge control signal while requesting a read or write burst allows you to specify
whether or not the controller should close (auto-precharge) the current opened page at the
end of the read or write burst.
Enable reordering
Turn on to allow the controller to perform command and data reordering to achieve the
highest efficency.
Starvation limit for each
command Specifies the number of commands that can be served before a waiting command is served.
The legal range is from 1 to 63.
Local-to-memory address
mapping
Allows you to control the mapping between the address bits on the Avalon interface and the
chip, row, bank, and column bits on the memory interface.
If your application issues bursts that are greater than the column size of the memory device,
choose the Chip-Row-Bank-Column option. This option allows the controller to use its
look-ahead bank management feature to hide the effect of changing the currently open row
when the burst reaches the end of the column.
On the other hand, if your application has several masters that each use separate areas of
memory, choose the Chip-Bank-Row-Column option. This option allows you to use the top
address bits to allocate a physical bank in the memory to each master. The physical bank
allocation avoids different masters accessing the same bank which is likely to cause
inefficiency, as the controller must then open and close rows in the same bank.