Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 46)

4–4 Chapter 4: Compiling and Simulating
Simulating the Design
External Memory Interface Handbook Volume 3 June 2011 Altera Corporation
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
f To attach the SignalTap
®
II logic analyzer to your design, refer to AN 380: Test DDR or
DDR2 SDRAM Interfaces on Hardware Using the Example Driver .
After you have compiled the example top-level file, you can perform RTL simulation
or program your targeted Altera device to verify the example top-level file in
hardware.
Simulating the Design
During system generation, SOPC Builder optionally generates a simulation model
and testbench for the entire system, which you can use to easily simulate your system
in any of Altera's supported simulation tools. The MegaWizard also generates a set of
ModelSim
®
Tcl scripts and macros that you can use to compile the testbench, IP
functional simulation models, and plain-text RTL design files that describe your
system in the ModelSim simulation software (refer to
“Generated Files” on page 2–8 ).
f For more information about simulating SOPC Builder systems, refer to volume 4 of
the Quartus II Handbook and AN 351: Simulating Nios II Embedded Processor Designs . For
more information about how to include your board simulation results in the Quartus
II software and how to assign pins using pin planners, refer to
ALTMEMPHY Design
Tutorials section in volume 5 of the External Memory Interface Handbook.
In ALTMEMPHY variations for DDR or DDR2 SDRAM interfaces, you have the
following simulation options:
■ Skip calibration—performs a static setup of the ALTMEMPHY megafunction to
skip calibration and go straight into user mode.
1
Skip calibration mode supports the default ALTMEMPHY
parameterization with CAS latency of 3 for DDR memory, and all CAS
latencies for DDR2 memory. The additive latency and registered DIMMs
must be disabled for all memory types.
1
Skip calibration is unavailable for DDR2 RDIMMs.
■ Quick calibration—performs a calibration on a single pin and chip select.
1 You may see memory model warnings about initialization times.
■ Full calibration—across all pins and chip selects. This option allows for longer
simulation time.
1 In quick and skip calibration modes, the ALTMEMPHY megafunction ignores any
delays, and assumes that all delays in the testbench and memory model are 0 ps. To
successfully simulate a design with delays in the testbench and memory model, you
must generate a full calibration mode model in the MegaWizard Plug-In Manager.
If you are simulating your ALTMEMPHY-based design with a Denali model, Altera
recommends that you use full calibration mode.
f For more information about simulation, refer to the Simulation section in volume 4 of
the External Memory Interface Handbook.