Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 62)

5–16 Chapter 5: Functional Description—ALTMEMPHY
Block Description
External Memory Interface Handbook Volume 3 June 2011 Altera Corporation
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
Reset Management
The reset management for Cyclone III devices is instantiated in the same way as it is
with Stratix II devices.
Stratix III and Stratix IV Devices
The clocking and reset block is responsible for clock generation, reset management,
and phase shifting of clocks. It also has control of clock network types that route the
clocks.
The ability of the ALTMEMPHY megafunction to work out the optimum phase
during calibration and to track voltage and temperature variation relies on phase
shifting the clocks relative to each other.
1 Certain clocks need to be phase shifted during the ALTMEMPHY megafunction
operation.
Clock management circuitry is implemented by using:
■ PLL
■ DLL
PLL
The ALTMEMPHY parameter editor automatically generates an ALTPLL
megafunction instance. The ALTPLL megafunction is responsible for generating the
different clock frequencies and relevant phases used within the ALTMEMPHY
megafunction.
The device families available have different PLL capabilities. The minimum PHY
requirement is to have 16 phases of the highest frequency clock. The PLL uses With
No Compensation
operation mode to minimize jitter. Changing the PLL
compensation mode may result in inaccurate timing results.
You must choose a PLL and PLL input clock pin that are located on the same side of
the device as the memory interface to ensure minimal jitter. Cascaded PLLs are not
recommended as jitter can accumulate, causing the memory output clock to violate
the memory device jitter specification. Also, ensure that the input clock to the PLL is
stable before the PLL locks. If not, you must perform a manual PLL reset (by driving
the global_reset_n signal low) and relock the PLL to ensure that the phase
relationship between all PLL outputs are properly set.
f
For more information about the VCO frequency range and the available phase shifts,
refer to the
Clock Networks and PLLs in Stratix III Devices chapter in volume 1 of the
Stratix III Device Handbook or the Clock Networks and PLLs in Stratix IV Devices chapter
in volume 1 of the Stratix IV Device Handbook.