Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 10)

1–4 Chapter 1: About This IP
Unsupported Features
External Memory Interface Handbook Volume 3 June 2011 Altera Corporation
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
Unsupported Features
The DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP do not support the
following features:
■ Timing simulation.
■ Burst length of 2.
■ Partial burst and unaligned burst in ECC and non-ECC mode when DM pins are
disabled.
MegaCore Verification
Altera performs extensive random, directed tests with functional test coverage using
industry-standard Denali models to ensure the functionality of the DDR and DDR2
SDRAM Controllers with ALTMEMPHY IP.
Memory burst length of 4 v
Memory burst length of 8 v
Built-in flexible memory burst adapter v
Configurable Local-to-Memory address mappings v
Optional run-time configuration of size and mode register settings, and
memory timing
v
Partial array self-refresh (PASR) v
Support for industry-standard DDR and DDR2 SDRAM devices; and DIMMs v
Optional support for self-refresh command v
Optional support for user-controlled power-down command —
Optional support for automatic power-down command with programmable
time-out
v
Optional support for auto-precharge read and auto-precharge write
commands
—
Optional support for user-controller refresh v
Optional multiple controller clock sharing in Qsys Flow v
Integrated error correction coding (ECC) function 72-bit v
Integrated ECC function, 16, 24, and 40-bit v
Support for partial-word write with optional automatic error correction v
Support for OpenCore Plus evaluation —
IP functional simulation models for use in Altera-supported VHDL and Verilog
HDL simulator
v
Note to Table 1–3 :
(1) HPC II supports additive latency values greater or equal to t
RCD
-1, in clock cycle unit (t
CK
).
Table 1–3. DDR and DDR2 SDRAM HPC and HPC II Features (Part 2 of 2)
Features HPC II