Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 33)

Chapter 3: Parameter Settings 3–7
ALTMEMPHY Parameter Settings
June 2011 Altera Corporation External Memory Interface Handbook Volume 3
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
Table 3–5. DDR2 SDRAM Timing Parameter Settings (Note 1) (Part 1 of 2)
Parameter Name Range Units Description
t
INIT
0.001–
1000
µs
Minimum memory initialization time. After reset, the
controller does not issue any commands to the memory
during this period.
t
MRD
2–39 ns
Minimum load mode register command period. The
controller waits for this period of time after issuing a load
mode register command before issuing any other
commands.
t
MRD
is specified in ns in the DDR2 SDRAM
high-performance controller and in terms of t
CK
cycles in
Micron's device datasheet. Convert t
MRD
to ns by
multiplying the number of cycles specified in the
datasheet times t
CK
, where t
CK
is the memory operation
frequency and not the memory device's t
CK
.
t
RAS
8–200 ns
Minimum active to precharge time. The controller waits
for this period of time after issuing an active command
before issuing a precharge command to the same bank.
t
RCD
4–65 ns
Minimum active to read-write time. The controller does
not issue read or write commands to a bank during this
period of time after issuing an active command.
t
RP
4–65 ns
Minimum precharge command period. The controller
does not access the bank for this period of time after
issuing a precharge command.
t
REFI
1–65534 µs
Maximum interval between refresh commands. The
controller performs regular refresh at this interval unless
user-controlled refresh is turned on.
t
RFC
14–1651 ns
Minimum autorefresh command period. The length of
time the controller waits before doing anything else after
issuing an auto-refresh command.
t
WR
4–65 ns
Minimum write recovery time. The controller waits for
this period of time after the end of a write transaction
before issuing a precharge command.
t
WTR
1–3 t
CK
Minimum write-to-read command delay. The controller
waits for this period of time after the end of a write
command before issuing a subsequent read command to
the same bank. This timing parameter is specified in clock
cycles and the value is rounded off to the next integer.
t
AC
300–750 ps DQ output access time from CK/CK# signals.
t
DQSCK
100–750 ps DQS output access time from CK/CK# signals.
t
DQSQ
100–500 ps
The maximum DQS to DQ skew; DQS to last DQ valid, per
group, per access.
t
DQSS
0–0.3 t
CK
Positive DQS latching edge to associated clock edge.