Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 18)

2–4 Chapter 2: Getting Started
Qsys Flow
External Memory Interface Handbook Volume 3 June 2011 Altera Corporation
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
1 Among the files generated by SOPC Builder is the Quartus II IP File (.qip).
This file contains information about a generated IP core or system. In most
cases, the .qip file contains all of the necessary assignments and
information required to process the MegaCore function or system in the
Quartus II compiler. Generally, a single .qip file is generated for each SOPC
Builder system. However, some more complex SOPC Builder components
generate a separate .qip file. In that case, the system .qip file references the
component .qip file.
10. Compile your design, refer to “Compiling and Simulating” on page 4–1 .
Qsys Flow
The Qsys flow allows you to add the DDR and DDR2 SDRAM high-performance
controllers directly to a new or existing Qsys system.
You can also easily add other available components to quickly create a Qsys system
with a DDR or DDR2 SDRAM controller, such as the Nios II processor and
scatter-gather direct memory access (SDMA) controllers. Qsys automatically creates
the system interconnect logic and system simulation environment.
f
For more information about Qsys, refer to volume 1 of the Quartus II Handbook. For
more information about how to use controllers with Qsys, refer to the ALTMEMPHY
Design Tutorials section in volume 6 of the External Memory Interface Handbook. For
more information on the Quartus II software, refer to the Quartus II Help.
Specifying Parameters
To specify the parameters for the DDR or DDR2 SDRAM Controller with
ALTMEMPHY IP, using the Qsys flow, perform the following steps:
1. In the Quartus II software, create a new Quartus II project with the New Project
Wizard .
2. On the Tools menu, click Qsys.
3. For a new system, specify the system name and language.
4. Add DDR or DDR2 SDRAM Controller with ALTMEMPHY to your system
from the System Contents tab.
1
The DDR or DDR2 SDRAM Controller with ALTMEMPHY is in the
SDRAM
folder under the Memories and Memory Controllers folder.
5. In the DDR or DDR2 SDRAM Controller with ALTMEMPHY parameter editor,
s pecify the required parameters on all pages in the Parameter Settings tab.
1 To avoid simulation failure, you must set Local-to-Memory Address
Mapping
to CHP-BANK-ROW-COL if you select High Peformance
Controller II for Controller Architecture.
f For detailed explanation of the parameters, refer to the “Parameter
Settings” on page 3–1 .