Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 61)

Chapter 5: Functional Description—ALTMEMPHY 5–15
Block Description
June 2011 Altera Corporation External Memory Interface Handbook Volume 3
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
Full rate
aux_half_rate_cl
k
C0 0

Half-Rate Global
The only half-rate clock
parameterizable for the
ALTMEMPHY megafunction to
be used by the controller. This
clock is not used in full-rate
controllers. This clock also
feeds into a divider circuit to
provide the PLL scan_clk
signal for reconfiguration.
phy_clk_1x
and
mem_clk_2x
and
aux_full_
rate_clk
C1 0

Full-Rate Global
Generates DQS signals and the
memory clock and to clock the
PHY in full-rate mode.
Half-rate
and full rate
write_clk_2x C2 -90

Full-Rate Global
Clocks the data (DQ) when you
perform a write to the memory.
Half-rate
and full rate
resynch_clk_2x C3 Calibrated Full-Rate Global
A full-rate clock that captures
and resynchronizes the
captured read data. The capture
and resynchronization clock has
a variable phase that is
controlled via the PLL
reconfiguration logic by the
control sequencer block.
Half-rate
and full rate
measure_clk_2x C4 Calibrated Full-Rate Global
This clock is for VT tracking.
This free-running clock
measures relative phase shifts
between the internal clock(s)
and those being fed back
through a mimic path. As a
result, you can track VT effects
on the FPGA and compensate
for them.
Half-rate
and full rate
ac_clk_2x —
0
, 90,
180
,
270

Full-Rate Global
This clock is derived from
mem_clk_2x
when you choose
0
 or 180 phase shift) or
write_clk_2x (when you
choose 90
 or 270 phase
shift), refer to “Address and
Command Datapath” on
page 5–3
.
Table 5–3. DDR/DDR2 SDRAM Clocking in Cyclone III Devices (Part 2 of 2) (Part 2 of 2)
Design
Rate
Clock Name
Post-Scale
Counter
Phase
(Degrees)
Clock
Rate
Clock
Network
Type
Notes