Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 53)

Chapter 5: Functional Description—ALTMEMPHY 5–7
Block Description
June 2011 Altera Corporation External Memory Interface Handbook Volume 3
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
Half-rate
and full rate
write_clk_2x C2 –90 Full-Rate Global
Clocks the data out of the
DDR I/O (DDIO) pins in
advance of the DQS strobe
(or equivalent). As a
result, its phase leads that
of the mem_clk_2x by
90°.
Half-rate
and full rate
mem_clk_ext_2x C3 > 0

Full-Rate Dedicated
This clock is only used if
the memory clock
generation uses dedicated
output pins. Applicable
only in HardCopy II or
Stratix II prototyping for
HardCopy II designs.
Half-rate
and full rate
resync_clk_2x C4 Calibrated Full-Rate Regional
Clocks the
resynchronization
registers after the capture
registers. Its phase is
adjusted to the center of
the data valid window
across all the
DQS-clocked DDIO
groups.
Half-rate
and full rate
measure_clk_2x C5 Calibrated Full-Rate Regional (2)
This clock is for VT
tracking. This free-running
clock measures relative
phase shifts between the
internal clock(s) and those
being fed back through a
mimic path. As a result,
the ALTMEMPHY
megafunction can track
VT effects on the FPGA
and compensate for the
effects.
Table 5–1. DDR/DDR2 SDRAM Clocking in Arria GX, HardCopy II, Stratix II, and Stratix II GX Devices (Part 2 of 3)
Design
Rate
Clock Name
Postscale
Counter
Phase
(Degrees)
Clock Rate
Clock
Network Type
Notes