Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP User Manual
Page 25
Chapter 2: Getting Started
2–11
Generated Files
June 2011
Altera Corporation
External Memory Interface Handbook Volume 3
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
alt_mem_ddrx_burst_tracking.v
Tracks data received per local burst command.
alt_mem_ddrx_dataid_manager.v
Manages the IDs associated with data stored in buffer.
alt_mem_ddrx_fifo.v
Contains the FIFO buffer to store local data to create a link; is also used
in rdata_path to store the read address and error address.
alt_mem_ddrx_list.v
Tracks the DRAM commands associated with the data stored
internally.
alt_mem_ddrx_rdata_path.v
Contains read data path logic.
alt_mem_ddrx_wdata_path.v
Contains write data path logic.
alt_mem_ddrx_define.iv
Defines common parameters used in the RTL files.
alt_mem_ddrx_ecc_decoder.v
Instantiates appropriate width ECC decoder logic.
alt_mem_ddrx_ecc_decoder_32_syn.v
Contains synthesizable 32-bit version of ECC decoder.
alt_mem_ddrx_ecc_decoder_64_syn.v
Contains synthesizable 64-bit version of ECC decoder.
alt_mem_ddrx_ecc_encoder.v
Instantiates appropriate width ECC encoder logic.
alt_mem_ddrx_ecc_encoder_32_syn.v
Contains synthesizable 32-bit version of ECC decoder.
alt_mem_ddrx_ecc_encoder_64_syn.v
Contains synthesizable 64-bit version of ECC decoder.
alt_mem_ddrx_ecc_encoder_decoder_wrapper.v Wrapper that instantiates all ECC logic.
alt_mem_ddrx_input_if.v
Contains local input interface logic.
alt_mem_ddrx_mm_st_converter.v
Contains supporting logic for Avalon-MM interface.
alt_mem_ddrx_rank_timer.v
Contains a timer associated with rank timing.
alt_mem_ddrx_sideband.v
Contains supporting logic for user-controlled refresh and precharge
signals.
alt_mem_ddrx_tbp.v
Contains command queue and associated logic for reordering
features.
alt_mem_ddrx_timing_param.v
Contains timer logic associated with nonrank timing.
alt_mem_ddrx_controller_st_top.v
Wrapper that instantiates all submodules amd configuration registers.
alt_mem_ddrx_controller_top.v
Wrapper that contains memory controller with Avalon-MM interface.
alt_mem_ddrx_controller.v
Wrapper that instantiates all submodules.
Table 2–5. Controller-Generated Files (Part 2 of 2)
Filename
Description