Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 118)

6–24 Chapter 6: Functional Description—High-Performance Controller II
Register Maps
External Memory Interface Handbook Volume 3 June 2011 Altera Corporation
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
Controller Register Map
The controller register map allows you to control the memory controller settings. To
access the controller register map, connect the CSR interface signals using the
Avalon-MM protocol.
Table 6–15 shows the register map for the controller.
0x006
2:0 Reserved 0 — Reserved for future use.
5:3 CWL — Read write
CAS write latency setting. The default value
for these bits is set by the MegaWizard CAS
Write Latency setting for your controller
instance. You must set this value in the CSR
interface register map 0x126 as well.
6 ASR 0 Read write Not used by the controller, but you can set
and program into the memory device mode
register.
7 SRT/ET 0 Read write
8 Reserved 0 — Reserved for future use.
10:9 RTT_WR 0 Read write
Not used by the controller, but you can set
and program into the memory device mode
register.
15:11 Reserved 0 — Reserved for future use.
17:16 MPR_RF 0 Read write Not used by the controller, but you can set
and program into the memory device mode
register.
18 MPR 0 Read write
31:19 Reserved 0 — Reserved for future use.
Table 6–14. ALTMEMPHY Register Map (Part 2 of 2)
Address Bit Name Default Access Description
Table 6–15. Controller Register Map (Part 1 of 5)
Address Bit Name Default Access Description
0x100
0 CAL_SUCCESS — Read only
This bit reports the value of the ALTMEMPHY
ctl_cal_success
output. Writing to this
bit has no effect.
1 CAL_FAIL — Read only
This bit reports the value of the ALTMEMPHY
ctl_cal_fail
output. Writing to this bit
has no effect.
2 CAL_REQ 0 Read write
Writing a 1 to this bit asserts the
ctl_cal_req
signal to the ALTMEMPHY
megafunction. Writing a 0 to this bit
deaaserts the signal, and the ALTMEMPHY
megafunction will then initiate its calibration
sequence.
You must not use this register during the
ALTMEMPHY megafunction calibration. You
must wait until the CAL_SUCCESS or
CAL_FAIL register shows a value of 1.
7:3 Reserved. 0 — Reserved for future use.
13:8 Reserved. 0 — Reserved for future use.
30:14 Reserved. 0 — Reserved for future use.