Arbiter, Arbitration rules, Rank timer – Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP User Manual
Page 97: Read data buffer, Write data buffer, Ecc block, Afi interface, Arbiter –3, Arbitration rules –3
Chapter 6: Functional Description—High-Performance Controller II
6–3
Memory Controller Architecture
June 2011
Altera Corporation
External Memory Interface Handbook Volume 3
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
Arbiter
The arbiter determines the order in which requests are passed to the memory device.
When the arbiter receives a single request, that request is passed immediately;
however, when multiple requests are received, the arbiter uses arbitration rules to
determine the order in which to pass requests to the memory device.
Arbitration Rules
The arbiter follows the following arbitration rules:
■
If only one master is issuing a request, grant that request immediately.
■
If there are outstanding requests from two or more masters, the arbiter applies the
following tests, in order:
a. Is there a read request? If so, the arbiter grants the read request ahead of any
write requests.
b. If neither of the above conditions apply, the arbiter grants the oldest request
first.
Rank Timer
The rank timer maintains rank-specific timing information, and performs the
following functions:
■
Ensures that only four activates occur within a specified timing window.
■
Manages the read-to-write and write-to-read bus turnaround time.
■
Manages the time-to-activate delay between different banks.
Read Data Buffer
The read data buffer receives data from the PHY and passes that data through the
input interface to the master.
Write Data Buffer
The write data buffer receives write data from the input interface and passes that data
to the PHY, upon approval of the write request.
ECC Block
The error-correcting code (ECC) block comprises an encoder and a decoder-corrector,
which can detect and correct single-bit errors, and detect double-bit errors. The ECC
block can remedy errors resulting from noise or other impairments during data
transmission.
AFI Interface
The AFI interface provides communication with the memory device, through the
physical layer logic (PHY).
For more information about AFI signals, refer to