Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 48)

5–2 Chapter 5: Functional Description—ALTMEMPHY
Block Description
External Memory Interface Handbook Volume 3 June 2011 Altera Corporation
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
Block Description
Figure 5–1 on page 5–2 shows the major blocks of the ALTMEMPHY megafunction
and how it interfaces with the external memory device and the controller. The
ALTPLL megafunction is instantiated inside the ALTMEMPHY megafunction, so that
you do not need to generate the clock to any of the ALTMEMPHY blocks.
The ALTMEMPHY megafunction comprises the following blocks:
■ Write datapath
■ Address and command datapath
■ Clock and reset management, including DLL and PLL
■ Sequencer for calibration
■ Read datapath
Figure 5–1. ALTMEMPHY Megafunction Interfacing with the Controller and the External Memory
External
Memory
Device
ALTMEMPHY
Write
Datapath
Address
and
Command
Datapath
Clock
and Reset
Management
Sequencer
Read
Datapath
Memory
Controller
User
Logic
PLL
FPGA
DLL