Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 71)

Chapter 5: Functional Description—ALTMEMPHY 5–25
Block Description
June 2011 Altera Corporation External Memory Interface Handbook Volume 3
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
Data Resynchronization
The read datapath block performs the following two tasks:
1. Transfers the captured read data (rdata[n]_1x) from the half-rate
resynchronization clock (resync_clk_1x) domain to the half-rate system clock
(phy_clk_1x) domain using DPRAM. Resynchronized data from the FIFO buffer is
shown as ram_data_1x.
2. Reorders the resynchronized data (ram_rdata_1x) into ctl_mem_rdata.
The full-rate datapath is similar to the half-rate datapath, except that the
resynchronization FIFO buffer converts from the full-rate resynchronization clock
domain (resync_clk_2x) to the full-rate PHY clock domain, instead of converting it to
the half-rate PHY clock domain as in half-rate designs.
Postamble Protection
A dedicated postamble register controls the gating of the shifted DQS signal that
clocks the DQ input registers at the end of a read operation. This ensures that any
glitches on the DQS input signals at the end of the read postamble time do not cause
erroneous data to be captured as a result of postamble glitches. The postamble path is
also calibrated to determine the correct clock cycle, clock phase shift, and delay chain
settings. You can see the process in simulation if you choose Full calibration (long
simulation time) mode in the MegaWizard Plug-In Manager.
f For more information about the postamble protection circuitry, refer to the External
Memory Interfaces in Stratix III Devices chapter in volume 1 of the Stratix III Device
Handbook and the External Memory Interfaces in Stratix IV Devices chapter in volume 1
of the Stratix IV Device Handbook.
Write Datapath
This topic describes the write datapath.
Arria GX, Arria II GX, Cyclone III, HardCopy II, Stratix II, and Stratix II GX
Devices
The write datapath logic efficiently transfers data from the HDR memory controller to
DDR SDRAM-based memories. The write datapath logic consists of:
■ DQ and DQ output-enable logic
■ DQS and DQS output-enable logic
■ Data mask (DM) logic
The memory controller interface outputs 4n-bit wide data (ctl_wdata[4n]) at half-rate
frequency.
Figure 5–9 shows that the HDR write data (ctl_wdata[4n]) is clocked by
the half-rate clock phy_clk_1x and is converted into SDR which is represented by
wdp_wdata_h
and wdp_wdata_l and clocked by the full-rate clock write_clk_2x.