Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 82)

5–36 Chapter 5: Functional Description—ALTMEMPHY
PHY-to-Controller Interfaces
External Memory Interface Handbook Volume 3 June 2011 Altera Corporation
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
For half-rate designs, the AFI allows the controller to issue reads and writes that are
aligned to either half-cycle of the half-rate phy_clk, which means that the datapaths
can support multiple data alignments—word-unaligned and word-aligned writes and
reads.
Figure 5–12 and Figure 5–13 display the half-rate write operation.
Figure 5–14 shows a full-rate write.
After calibration completes, the sequencer sends the write latency in number of clock
cycles to the controller.
Figure 5–12. Half-Rate Write with Word-Unaligned Data
Figure 5–13. Half-Rate Write with Word-Aligned Data
Figure 5–14. Full-Rate Write
00 11 00 01
00
11 01 10 00
-- a x cb xd
ctl_clk
ctl_dqs_burst
ctl_wdata_valid
ctl_wdata
00
10 11 00
00 11 00
-- ba -- dc
ctl_clk
ctl_dqs_burst
ctl_wdata_valid
ctl_wdata
-- a -- b
ctl_clk
ctl_dqs_burst
ctl_wdata_valid
ctl_wdata