Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 129)

June 2011 Altera Corporation External Memory Interface Handbook Volume 3
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
8. Timing Diagrams
This chapter shows timing diagrams for the DDR and DDR2 SDRAM
high-performance controllers II (HPC II).
DDR and DDR2 High-Performance Controllers II
This section discusses the following timing diagrams for HPC II:
■ “Half-Rate Read”
■ “Half-Rate Write”
■ “Full-Rate Read”
■ “Full-Rate Write”