Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 16)

2–2 Chapter 2: Getting Started
SOPC Builder Flow
External Memory Interface Handbook Volume 3 June 2011 Altera Corporation
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
The SOPC Builder flow offers the following advantages:
■ Generates simulation environment
■ Creates custom components and integrates them via the component wizard
■ Interconnects all components with the Avalon-MM interface
The MegaWizard Plug-In Manager flow offers the following advantages:
■ Allows you to design directly from the DDR or DDR2 SDRAM interface to
peripheral device or devices
■ Achieves higher-frequency operation
SOPC Builder Flow
The SOPC Builder flow allows you to add the DDR and DDR2 SDRAM
high-performance controllers directly to a new or existing SOPC Builder system.
You can also easily add other available components to quickly create an SOPC Builder
system with a DDR or DDR2 SDRAM controller, such as the Nios II processor and
scatter-gather direct memory access (SDMA) controllers. SOPC Builder automatically
creates the system interconnect logic and system simulation environment.
f
For more information about SOPC Builder, refer to volume 4 of the Quartus II
Handbook. For more information about how to use controllers with SOPC Builder,
refer to
the ALTMEMPHY Design Tutorials section in volume 5 of the External Memory
Interface Handbook. For more information on the Quartus II software, refer to the
Quartus II Help.
Specifying Parameters
To specify the parameters for the DDR or DDR2 SDRAM Controller with
ALTMEMPHY IP, using the SOPC Builder flow, perform the following steps:
1. In the Quartus II software, create a new Quartus II project with the New Project
Wizard .
2. On the Tools menu, click SOPC Builder.
3. For a new system, specify the system name and language.
4. Add DDR or DDR2 SDRAM Controller with ALTMEMPHY to your system
from the System Contents tab.
1 The DDR or DDR2 SDRAM Controller with ALTMEMPHY is in the
SDRAM
folder under the Memories and Memory Controllers folder.
5. Specify the required parameters on all pages in the Parameter Settings tab.
1 To avoid simulation failure, you must set Local-to-Memory Address
Mapping
to CHP-BANK-ROW-COL if you select High Peformance
Controller II for Controller Architecture.
f For detailed explanation of the parameters, refer to the “Parameter
Settings” on page 3–1 .