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Rainbow Electronics DS3134 User Manual

Page 98

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DS3134

98 of 203

8.1 RECEIVE SIDE

8.1.1 OVERVIEW

The receive DMA uses a scatter gather technique to write packet data into main memory. The Host will
keep track of and decide where the DMA should place the incoming packet data. There are a set of
descriptors that is handed back and forth between the DMA and the Host. Via these descriptors, the Host
can inform the DMA where to place the packet data and the DMA can tell the Host when the data is ready
to be processed.

The operation of the receive DMA has three main areas as shown in Figures 8.1.1A and 8.1.1B and
Table 8.1.1A. The Host will write to the Free Queue Descriptors informing the DMA where it can place
the incoming packet data. Associated with each free data buffer location is a free Packet Descriptor
where the DMA can write information to inform the Host about the attributes of the packet data (i.e.
status information, number of bytes, etc.) that it will output. To accommodate the various needs of packet
data, the Host can quantize the free data buffer space into two different buffer sizes. The Host will set the
size of the buffers via the Receive Large Buffer Size (RLBS) and the Receive Small Buffer Size (RSBS)
registers.

Register Name:

RLBS

Register Description: Receive Large Buffer Size Select
Register Address:

0790h

7

6

5

4

3

2

1

0

LBS7

LBS6

LBS5

LBS4

LBS3

LBS2

LBS1

LBS0

15

14

13

12

11

10

9

8

n/a

n/a

n/a

LBS12

LBS11

LBS10

LBS9

LBS8

Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.

Bits 0 to 12 / Large Buffer Select Bit (LBS0 to LBS12).

0000000000000 (0000h) = Buffer Size is 0 Bytes
1111111111111 (1FFFh) = Buffer Size is 8191 Bytes

Register Name:

RSBS

Register Description: Receive Small Buffer Size Select
Register Address:

0794h

7

6

5

4

3

2

1

0

SBS7

SBS6

SBS5

SBS4

SBS3

SBS2

SBS1

SBS0

15

14

13

12

11

10

9

8

n/a

n/a

n/a

SBS12

SBS11

SBS10

SBS9

SBS8

Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.