Rainbow Electronics DS3134 - Manual (Page 174)

DS3134
174 of 203
Figure 10.3D
16-Bit Write (only upper 8-bits active) Cycle
Intel Mode (LIM = 0)
Arbitration Disabled (LARBE = 0)
Bus Transaction Time = Timed from LRDY* (LRDY = 0000)
Note: The LRDY* signal must be detected by the 9th LCLK or the bus access attempted by the Host will
be unsuccessful and the LBE status bit will be set.
lb_pi1_v2
10.3D
03/22/99
LCLK
LA[19:0]
LD[7:0]
LD[15:8]
LWR*
LRD*
Address Valid
LBHE*
LRDY*
Data Valid
1 2 3 4 5 6 7 8 9 10