Rainbow Electronics DS3134 - Manual (Page 156)

DS3134
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Read only bits in the PDCM register are indicated above by being underlined. All other bits are read-
write.
Bit 0 / Memory Space Indicator (MSI). This read only bit is forced to zero to indicate that the internal
device configuration registers are mapped to memory space.
Bits 1 & 2 / Type 0 & Type 1. These read only bits are forced to 00b to indicate that the internal device
configuration registers can be mapped anywhere in the 32 bit address space.
Bit 3 / Prefetchable (PF). This read only bit is forced to zero to indicate that prefetching is not supported
by the device for the internal device configuration registers.
Bits 4 to 11 / Base Address. These read only bits are forced to zero to indicate that the internal device
configuration registers require 4k bytes of memory space.
Bits 12 to 31 / Base Address. These read/write bits define the location of the 4k memory space that is
mapped to the internal configuration registers. These bits correspond to the most significant bits of the
PCI address space.
Register Name: PINTL0
Register Description: PCI Interrupt Line & Pin / Minimum Grant / Maximum Latency Register 0
Register Address:
0x03Ch
lsb
Interrupt Line
Interrupt Pin (Read Only / set to 01h)
Minimum Grant (Read Only / set to 05h)
msb
Maximum Latency (Read Only / set to 0Fh)
Bits 0 to 7 / Interrupt Line. These read/write bits indicate and store interrupt line routing information.
The device does not use this information; it is only posted here for use by the Host.
Bits 8 to 15 / Interrupt Pin. These read only bits are forced to 01h to indicate that the uses PINTA* as
an interrupt.
Bits 16 to 23 / Minimum Grant. These read only bits are used to indicate to the Host, how long of a
burst period the device needs assuming a clock rate of 33 MHz. The value placed in these bits specifies a
period of time in 0.25 us increments. These bits are forced to 05h.
Bits 24 to 31 / Maximum Latency. These read only bits are used to indicate to the Host, how often the
device needs to gain access to the PCI bus. The value placed in these bits specifies a period of time in
0.25 us increments. These bits are forced to 0Fh.