Rainbow Electronics DS3134 - Manual (Page 27)

DS3134
27 of 203
Signal Name: LCLK
Signal Description: Local Bus Clock [PCI Bridge Mode Only]
Signal Type: Output (tri-state capable)
This signal outputs a buffered version of the clock applied at the PCLK input. All Local Bus signals are
generated and sampled from this clock. This output is tri-stated when the Local Bus is in the
Configuration Mode (LMS = 1). It can be disabled in the PCI Bridge Mode via the Local Bus Bridge
Mode Control Register (LBBMC).
Signal Name: LCS*
Signal Description: Local Bus Chip Select [Configuration Mode Only]
Signal Type: Input
This active low signal must be asserted for the device to accept a read or write command from an external
host. This signal is ignored in the PCI Bridge Mode (LMS = 0) and should be tied high.
2.4 JTAG SIGNAL DESCRIPTION
Signal Name: JTCLK
Signal Description: JTAG IEEE 1149.1 Test Serial Clock
Signal Type: Input
This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge. If not
used, this signal should be pulled high.
Signal Name: JTDI
Signal Description: JTAG IEEE 1149.1 Test Serial Data Input
Signal Type: Input (with internal 10k pull up)
Test instructions and data are clocked into this signal on the rising edge of JTCLK. If not used, this signal
should be pulled high. This signal has an internal pull-up.
Signal Name: JTDO
Signal Description: JTAG IEEE 1149.1 Test Serial Data Output
Signal Type: Output
Test instructions are clocked out of this signal on the falling edge of JTCLK. If not used, this signal
should be left open circuited.
Signal Name: JTRST*
Signal Description: JTAG IEEE 1149.1 Test Reset
Signal Type: Input (with internal 10k pull up)
This signal is used to asynchronously reset the test access port controller. At power up, JTRST must be
set low and then high. This action will set the device into the boundary scan bypass mode allowing
normal device operation. If boundary scan is not used, this signal should be held low. This signal has an
internal pull-up.