Rainbow Electronics DS3134 - Manual (Page 176)

DS3134
176 of 203
Figure 10.3F
8-Bit Write Cycle
Motorola Mode (LIM = 1)
Arbitration Enabled (LARBE = 1)
Bus Transaction Time = 6 LCLK (LRDY = 0110)
An attempted access by the Host causes the Local Bus to request the bus. If bus access has not been
granted (LBGACK* deasserted), then the timing shown at the top of the page will occur with LBR* being
asserted and then once LBG* is detected, the Local Bus will grab the bus for 32 to 1048576 clocks and
then release it. If the bus has already been granted (LBGACK* asserted), then the timing shown at the
bottom of the page will occur.
Note: LA / LD / LBHE* / LDS* / LR/W* are tri-stated.
LCLK
LBR*
LBG*
LBGACK*
32 to 1048576 LCLKs
lb_pm
LA[19:0]
LD[7:0]
LD[15:8]
LR/W*
LDS*
Address Valid
Data Valid
LBHE*
tri-state
tri-state
tri-state
tri-state
tri-state
tri-state
LCLK
1 2 3 4 5 6